EEPROM arrays are utilized for storage of data Typically, the data stored therein can be changed, either by programming or erasing, multiple times over the lifetime of the array. As in all non-volatile memory arrays, each cell is individually programmed; however, in contrast to either erasable, programmable read only memory (EPROM) or FLASH arrays, in EEPROM arrays each cell can also be individually erased.
Typical memory uses a single bit per cell, wherein electrical charge is stored on the floating gate of each cell. Within each cell, two possible voltage levels exist. The levels are controlled by the amount of charge that is stored on the floating gate; if the amount of charge on the floating gate is above a certain reference level, the cell is considered to be in a different level. Accordingly, each cell is characterized by a specific threshold voltage (Vt). Programming the cell increases threshold voltage Vt, whereas erasing the cell decreases threshold voltage Vt.
Non-volatile memory arrays comprise rows and columns of memory cells connected to word lines (rows of the array) and bit lines (columns). Each memory cell is connected to one word line and at least one bit line. Another terminal of the memory cell is connected either to another bit line (in which case, one of the bit lines is called the drain line and the other is the source line), or to a common line, such as a common source ground, depending on the array architecture. Programming or erasing an individual cell requires application of certain voltages to the word line and bit lines.
Generally, when programming or erasing a cell, one or more of the neighboring cells may also be affected by the programming/erasing operation, causing thereto a possible change in their threshold voltage. This unwanted change in threshold voltage of unselected cells is known in the art as the disturb problem, herein a “disturb”. A similar effect also occurs during a read operation. However, due to the relative weakness of the applied voltage levels, the effect is significantly smaller.
A standard prior art solution to the disturb problem in EEPROM arrays is to use two transistors per memory bit of the array, i.e., in addition to the memory transistor, a select transistor is also incorporated per cell. The select transistor usually disconnects the drain of the unselected memory transistors from the drain voltages used in the programming/erasing operations. The use of a select transistor per cell, however, significantly increases the area of the memory array.